The disclosed subject matter is directed generally to power control in a wireless communication device and, more particularly, to a system and method for calibration of open-loop power control in a wireless communication device.
Wireless communication devices are widely used throughout the world. Such wireless devices use radio frequency components, including transmitters and receivers. Proper operation of wireless devices requires the careful calibration of the transmitter and receiver sections. This is particularly important in some wireless communications schemes, such as code division multiple access (CDMA) technology where multiple users are transmitting simultaneously on the same frequency.
As is known in the art, CDMA technology assigns different pseudo noise (PN) codes to each wireless device. The PN codes are mathematically uncorrelated to each other such that one CDMA wireless device cannot decode the radio frequency (RF) signal intended for another CDMA device. As a result, a signal transmitted from one CDMA wireless device appears as noise to other CDMA devices operating at the same frequency and in the same geographic region. Thus, it is desirable to minimize transmitted power for each CDMA device in order to reduce the noise effects on other CDMA devices. Therefore, proper calibration of each CDMA device is important for satisfactory operation of the overall CDMA system.
A simplified block diagram of the receiver portion of a CDMA device is illustrated in the function block diagram of FIG. 1. The operation of the wireless device 10 illustrated in the functional block diagram of FIG. 1 is known to those of ordinary skill in the art and thus need not be described in great detail herein. Radio signals are detected by an antenna 12 and coupled to an RF stage 14. The RF stage 14 may include a number of different components, such as amplifiers, tuning circuitry, filters, and the like. For the sake of brevity, those various components are illustrated in FIG. 1 as the RF stage 14. The output of the RF stage 14 is coupled to an intermediate frequency (IF) stage 16. The RF stage 14 and IF stage 16 amplify the signal detected by the antenna 12 and shift the frequency from RF frequencies down to an intermediate frequency.
A variable gain amplifier (VGA) 18 receives the signal from the IF stage 16 and amplifies the signal to a desired level. As will be described in greater detail below, the variable gain amplifier has a variable gain input VCONT which sets the level of amplification. Although the VGA 18 is illustrated as a single component, a typical implementation often uses multiple stages of amplification to provide the necessary gain. However, these are engineering implementations within the skill of the design engineer. For the sake of simplicity, the multiple gain stages are illustrated in FIG. 1 as the VGA 18.
The output of the VGA 18 is coupled to a demodulator 19. The demodulator 19 comprises quadrature mixers 20 and 22. The quadrature mixer 20 is mixed with a local oscillator ILO while the quadrature mixer 22 is mixed with the local oscillator QLO. The output of the quadrature mixers 20 and 22 are taken for further processing in a conventional manner to produce the voice signal. However, the presently disclosed subject matter is directed to control of amplifiers and is not directly related to the actual processing of the received signals to produce the audio data.
The output of the quadrature mixers 20 and 22 are also coupled to low-pass filters 24 and 26, respectively, and subsequently coupled to inputs of respective analog-to-digital converters (ADC) 28 and 30. To efficiently utilize the dynamic range of the ADCs 28 and 30, the device 10 is designed to control the gain of the VGA 18 so as to produce a fixed power level at the inputs of the ADCs 28 and 30.
The outputs of the ADCs 28 and 30 are provided to an automatic gain control (AGC) loop 31 that ultimately will control the gain of the VGA 18. The outputs of the ADCs 28 and 30 are combined in a summing circuit 32 and provided to a log circuit 34. The log circuit 34 converts the signal from a linear form to a logarithmic form to thereby permit control of the VGA 18 in decibels (dB). The output of the log circuit 34 is combined with a control voltage PREF in an adder 36. The control voltage PREF is a control setpoint for the AGC loop 31.
The output of the adder 36 is integrated by an integrator 38 and provided as an input to a linearizer 40. The integrator 38 averages the control signal from the adder 36 and controls the response time of the AGC loop 31 through the selection of an integration time. It is also possible to control the bandwitdth of the AGC loop 31 by varying the gain of the integrator 38. An increase of the gain of the integrator 38 causes a corresponding increase in the bandwidth of the AGC loop 31. So long as the VGA 18 is properly linearized, the output of the integrator 38 is a linear function of the power-in (PIN) detected by the RF stage 14 and IF stage 16. The output of the integrator 38 is also an indication of the strength of the received signal. The signal is generally described in the wireless communication industry as a received signal strength indicator (RSSI).
Although the RSSI is an indicator of received signal strength, the signal itself cannot be used directly to control the gain of the VGA 18 because of the inherent nonlinearities of the variable gain input. As will be discussed in greater detail below, the linearizer 40 compensates for non-linearities in the control voltage versus gain characteristics of the VGA 18. The output of the linearizer 40 is provided to a digital-to-analog circuit (DAC) 42. The output of the DAC 42 is the control voltage VCONT that controls the gain of the VGA 18.
As noted above, it is desirable to produce fixed level inputs for the ADCs 28 and 30. The gain of the VGA 18 is controlled by the AGC loop 31 to provide the desired level at the inputs of the ADCs 28 and 30. FIG. 2 illustrates the ideal gain of the VGA 18 versus input power produced by the IF stage 16. FIG. 2 illustrates the ideal linear relationship between gain and power in (PIN). In an ideal situation, if PIN decreases, the gain of the VGA 18 increases by the same amount such that the power provided to the ADCs 28 and 30 is constant. Unfortunately, the variable gain input versus gain of the VGA 18 is not linear.
FIG. 3 illustrates the relationship between the control voltage VCONT and the gain of the VGA 18. The ideal curve shows a linear relationship between the control voltage VCONT and the gain. However, process variations and design limitations of the VGA 18 make it virtually impossible to achieve ideal linear relationship. FIG. 3 also illustrates the actual relationship between the control voltage VCONT and gain of the VGA 18. The actual curve has been somewhat exaggerated to illustrated the nonlinearity between the control voltage VCONT and gain. Because of this inherent nonlinearity, it is necessary to utilize the linearizer 40 to compensate for differences between the actual control voltage curve and the ideal voltage curve.
It should be noted that the non-linearity described herein refers to the nonlinear relationship between the voltage control VCONT and the actual gain of the VGA 18. The relationship between the input and output of the VGA 18 is highly linear. That is, the output of the VGA 18 is a highly accurate amplified version of the input. The non-linearity referred to herein is the nonlinear relationship between the voltage control input and the gain setting of the VGA 18.
As noted above, the linearizer 40 is used to compensate for nonlinearities in the gain control of the VGA 18. A number of different known techniques may be used to implement the linearizer 40. One such technique utilizes piece-wise linear segments, also illustrated in FIG. 3, to approximate the actual control voltage VCONT versus gain curve. In this manner, the device 10 selects the linear segment that most closely approximates the desired control voltage. For example, FIG. 3 illustrates a desired gain G1. In the ideal circumstance, a control voltage VCONT1 is required to generate that gain using the VGA 18 (see FIG. 1). However, due to the non-linearities in the gain control of the VGA 18, it is necessary to produce the control voltage Vxe2x80x2CONT1 to achieve the desired gain G1. Using the linearizer 40, the device 10 selects a linear segment 44 that approximates the desired control voltage Vxe2x80x2CONT1. With the proper selection of a linear line segment that approximates the desired control voltage, it is possible to accurately produce the desired level of gain in the VGA 18.
It should be noted that, for the sake of clarity, FIG. 3 illustrates a relatively few number of line segments, including the segment 44, to approximate the actual control voltage VCONT versus gain. To produce the desired degree of accuracy, it is generally necessary to produce significantly greater number of line segments to approximate the actual control voltage curve. In one example, sixteen separate segments are used to approximate the control voltage curve.
The drawback of this process is that each individual wireless device must be carefully calibrated so that the linearizer 40 is customized for virtually every device. This requires careful calibration of the receiver circuitry using external test equipment and programming of the linearizer 40 to achieve the desired degree of accuracy. Furthermore, the transmitter section of a wireless device, which is not illustrated in FIG. 1, has a similar variable gain amplifier. The control voltage curve of the transmitter variable gain amplifier must also be calibrated so that the transmit power is carefully controlled.
Because of the importance of power control in a CDMA wireless system, the calibration of the variable gain amplifier in the transmitter of a wireless device is even more important and time-consuming than the process described above with respect to the receiver portion of a wireless communication device. Thus, accurate calibration of each wireless device requires a significant number of calibration steps using external test equipment to generate a custom selected linearizer for the transmitter and receiver of each wireless device. As those skilled in the art will recognize, this is a time-consuming process, which is difficult to perform.
Using conventional techniques, each wireless device undergoes a number of calibration steps to assure proper operation of the variable gain amplifiers and linear operation for a wide range of gain settings over temperature and frequency. For a wireless device with multiple gain steps, such as a CDMA wireless device, the receiver portion may require nearly three dozen calibration steps while the transmitter portion of the wireless device may require as many as 117 different calibration steps. These processes include calibration steps for the variable gain amplifiers, including steps to assure linearity over frequency, over voltage variations of the power supply (not shown) and over the expected temperature range of operation.
Those skilled in the art will appreciate that such an enormous number of calibration steps, each of which requires external test equipment, is very time-consuming in the production process and adds significantly to the cost of the product. Therefore, it can be appreciated that there is a significant need for a technique that reduces the number of calibration steps that must be performed for proper operation of a wireless device. The presently disclosed subject matter provides this and other advantages as will be apparent from the following detailed description and accompanying figures.
The presently disclosed subject matter is embodied in a system and method for the control of transmit power in a wireless communication device. Wireless communication device has a transmitter and a receiver, which may share some circuit components. The system comprises a variable gain transmitter amplifier having an amplifier input and an amplifier output in a variable gain control input. A transmit power processor coupled to the amplifier output detects a transmit power level and generates a feedback signal related thereto. A power control reference circuit generates a power control signal indicative of a desired transmit power and comprises an open-loop gain component and a closed-loop gain component. An error circuit compares the feedback signal and the power control signal to generate an error signal. The error signal is coupled to the variable gain control input to maintain the transmit power level at the desired transmit power level.
In one embodiment, the system further comprises a received signal strength circuit to generate a received signal strength indicator indicative of a received signal strength of a radio signal received by the receiver. The open-loop gain component is based, at least in part, on the received signal strength indicator. The open-loop gain component may further comprise a pre-determined additional power gain wherein the power control signal comprises the received signal strength indicator and the pre-determined additional power gain.
The closed-loop gain component is based on a power control command received by the receiver. In this embodiment, the error signal is based at least in part on the closed-loop gain component controlled by the power control command received by the receiver.
The wireless communication device includes an antenna and the system may further comprise a radio frequency (RF) power amplifier having an RF amplifier input and an RF amplifier output and an RF amplifier gain control. The RF amplifier input is coupled to the variable gain transmitter amplifier output. The RF amplifier output is coupled to the antenna and the RF amplifier gain input is coupled to the error signal. In one embodiment, the RF amplifier gain is controlled in incremental steps. In this embodiment, the system further comprises a transmit power control circuit to generate a step gain control signal, based on the error signal, to control the incremental gain steps of the RF amplifier.
The system may further include log circuits to allow control of the system in decibels. In one embodiment, the transmit power processor comprises a log circuit to generate a feedback signal in decibels. The error signal may also be coupled to the variable gain control input via a log circuit to provide control of the variable gain transmitter amplifier in decibels.